Japanese

Reliability & Security

Circuit & System Mechanism with High Field Reliability

With miniaturization of CMOS devices, transistor aging which results in performance degradation becomes a crucial issue in highly reliable systems. Reliability-aware design could resolve this problem where some timing margin is added according to aging estimation. However, the worst case estimation to ensure the reliability would add excessive margin and incur appreciable performance degradation. On-line testing to predict or detect failures is a promising approach to avoid a sudden system down and guarantee high system reliability. We propose a novel failure prediction system that predicts failures based on accurate delay measurements for system-on-chips (SoC)s in the field.

The proposed system realizes accurate and efficient failure prediction with combination of a delay measurement at each core and a SoC test controller that schedules and manages core delay measurements and predicts failures in cores. Major challenges of the proposed system are (1) accuracy - delay measurement should be accurate under temperature and voltage variations, (2) coverage - delay measurement should cover a large number circuit elements, (3) limited test application-time - there are several test chances during a long lifetime, but a period of each test chance is quite short, and (4) priority - cores or parts of cores to be tested should be selected according to their degradation degrees. Tackling these issues, the proposed system realizes truly accurate and efficient failure prediction for SoCs.

DART

High Reliable Memory Architecture

Embedded memory is occupying the most area in SoCs. The continuous scaling of nano-device technology makes memory more susceptible to errors. Also, aging-induced faults manifest in field, which is a concern as causes of errors along with soft errors. Hence, reliability of memory is crucial to overall reliability of SoCs.

Our first work enhances reliability through an adaptive combination of repair and memory word correction. It is expanded in the second work to further enhance the reliability of memory using a more sophisticated test that can identify not only faulty memory cells, but aged ones as well. We propose a novel method that adaptively assigns aged and faulty words to functional repair or correction based on their vulnerabilities. ( Publications )

Hardware Trojan Detection

The outsourcing of numerous stages of the IC manufacturing process to foundries over which perfect control and oversight cannot be guaranteed has resulted in the security risk imposed by Hardware Trojans (HT) increasingly assuming realistic dimensions. HT, the malicious addition and/or modification of existing circuit elements can be exploited by a knowledgeable adversary to cause incorrect results, steal sensitive data, or even incapacitate a chip. Indeed, traditional test methods fall short in revealing hardware Trojans, as they are intended towards identifying modeled defects and, therefore, cannot disclose unmodeled malicious inclusions.

The sensitive identification and detection of hardware Trojans in ICs without a golden reference constitutes a key challenge. Traditional circuit partitioning and side-channel analysis techniques fall short of perfect sensitivity and accuracy and rely on golden references. In our work, a novel layout-aware clock tree driven circuit partitioning is coupled with an algorithm that selects transition delay fault test patterns that will deliver equal power on partitions. The circuit partitioning through the clock tree results in minimal hardware additions that can be effected through ECO. The selection of pairs of power uniform small regions results in reduction of inter-die variation effects, thus delivering increased detection sensitivity. The comparison for equal power of numerous pairs thoroughly perturbs the circuit under various activation conditions, resulting in elevated sensitivity and accuracy while obviating the need for reliance on Golden ICs. ( Publications )