Japanese

Decimal Computing

Decimal Computing

Decimal arithmetic using software is slow for very large-scale applications, while hardware based solution requires extra area overhead. A balanced strategy with software-hardware co-design can provide several Pareto points to the development of embedded systems in terms of hardware cost and performance.

We proposed Pareto points for software-hardware co-design-based decimal multiplication methods. The proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In the methods, software with some area-efficient binary and decimal component (hardware) is used to design the multiplication process. Analysis in different platforms, including our proposed integrated evaluation framework, reveals that the proposed methods provide several Pareto points for decimal multiplication solutions.

We also developed an integrated open source framework to design and evaluate such co- design-based decimal multiplication. The framework can realize cycle-accurate analysis for performance as well as hardware overhead for co-design solutions for decimal multiplication. In a software-hardware co-design solution, a part of the solution requires dedicated hardware. In the evaluation framework, new customized binary instruction as well as decimal oriented instructions supported by an accelerator to design and evaluate decimal multiplication are developed. The framework customizes the RISC-V ecosystem, IBM decNumber library, and test database for functional and performance verification. Besides the customization, a set of programs is developed to manage the framework and generating the necessary test program.